Area-efficient designs for modern microprocessors, DSP's (Digital Signal Processors), SoC's (System-on-Chip) in wearables, IoTs (Internet-of-Things), smartphones, tablets, laptops, and servers, etc., are increasingly becoming a critical factor due to the following requirements: reducing silicon cost, decreasing PCB (Printed Circuit Board) footprint, improving time-to-market (TTM), and slower scaling cadence of process technology node. These requirements all need to be met while meeting the stringent frequency and/or performance targets and power/leakage budgets.
Time borrowing flip-flops have been traditionally used in delay critical timing paths of high performance microprocessors and DSP's circuits to improve frequency and timing convergence. These flip-flops can reduce/remove process variation tax, clock skew/jitter tax, or fix timing violations resulting in higher operating frequency. The high operating frequency gain can easily be converted into lower power by reducing the supply voltage. The time borrowing flip-flops are designed by inserting clock inverters between master and slave latches by delaying the master latch. This results in time borrowing window which can be used to improve circuit performance. The delaying of master worsens the hold time of time borrowing flip-flop and requires min delay buffer insertion resulting in area and routing overhead.